The present invention relates to the field of semiconductor technology. Specifically, embodiments of the invention are directed to device structures and methods of manufacturing for the LDMOS (Laterally-Diffused Metal Oxide Semiconductor) device.
With the development of the ultra-large scale integrated circuit (ULSI), device size and supply voltage continue to be reduced. In technologies with minimum device dimensions larger than 28 nm, the breakdown voltage of laterally diffused metal oxide semiconductor (LDMOS) devices needs to be greater than 10V. For conventional LDMOS devices, in order to make the breakdown voltage greater than 10 V, shallow trench isolation (STI) structures are often introduced in the active region between the gate and the drain. However, the inventor has discovered that STI structures are not conducive to epitaxially grown recessed STI source/drain structures often used in FinFET (Fin Field Effect Transistor) devices under the 14 nm technology node.
In addition, the inventor has also discovered that, with the further shrinking of device size, dishing effects in the chemical mechanical polishing (CMP) process and micro-loading effects in the epitaxial growth process are becoming serious problems. Typically, the gate length of small devices is limited to less than 0.2 um, but in the LDMOS device, in order to ensure the breakdown voltage is large enough, the gate length is often more than the minimum length, resulting in dishing problems in the CMP process.